^^^ Yes, I guess I did ask that question before. Never got an answer, except some hand waving...

OK, it seems like we can view the FET on a 3d plot, with Id as a function of Vds and Vgs. So Id= f(Vds, Vgs) would be a "surface plot", the height of which is the current, Id. If we bias the FET so it has say, 1/2 Vdd on the gate, and put a current source as the source resistor, this will put us at a particular point on the surface. If done properly, Vgs will be approximately -1/2 Vco (cut off voltage), so the FET is approximatly "half on".

Ok, here is the claim: If we take a slice with Id fixed, Vds should be a (locally) linear function of Vgs. So, taking an (AC coupled) output from the source of the FET will give a signal (locally) linearly varying in Vgs.

Why is it linear? I need a mathematical model of the FET to figure this out. Note that if we fix Vds, the model Id vs. Vgs is *quadratic*. So it seems that (roughly speaking) for a fixed source resistor, we're taking a local linear approximation to a quadratic, so that will introduce distortion. The above will be an improvement if we can show it is really a linear curve, not a local linear approximation of a quadratic.

Let us all know if you (or anyone else) get mathematical formulas to justify the above reasoning. It should be possible to analyze the above cases with some simple algebra.

Well, that said, I just epoxied "collettes" for my Studio projects C4 mics. I used a single (self-biased) FET (K596 C0J, extract from Transsound TSB-120A capsules). I used a zener diode to drop 6.8V off the 40V or so input from the phantom adapter. A very simple circuit, but should do for now.

Richard