Topic: Capsule amplifier in electret microphone

[SparkE!]

Great!

Why R4/R5 = 10k? With C4/C5 lower cutoff frequency = 34 Hz. Should I increase the resistors or the capacitors for a lower cutoff frequency?

I reduced R4 and R5 to set the DC bias point of the second amplifier stage.  If you want a lower cutoff frequency, increase the size of the coupling caps, C3 and C4.  Also please note that C5 and V2 are the signal equivalent of the electret mic element.  I put them in to be able to run the SPICE simulation.

You still will not have a lot of signal level out of this because there's not a lot of gain.  The main things you are getting with this topology is a lower source impedance and balanced output.  You may need to add a third amplifier stage if you need more signal level.  I guess you'll find that out when you hook it up though...

[Roger Gustavsson]

You still will not have a lot of signal level out of this because there's not a lot of gain.  The main things you are getting with this topology is a lower source impedance and balanced output.  You may need to add a third amplifier stage if you need more signal level.  I guess you'll find that out when you hook it up though...

Another DIY:er made an simulation of the Helmke circuitry. I think the gain was about 1.5 times. That will correspond to 12 mV/94 dB. A lot more than the original 1.6 mV. The noisy floor of my soundcard, would probably not be a problem then. Your circuitry have perhaps simular gain?

Roger

[SparkE!]

You still will not have a lot of signal level out of this because there's not a lot of gain.  The main things you are getting with this topology is a lower source impedance and balanced output.  You may need to add a third amplifier stage if you need more signal level.  I guess you'll find that out when you hook it up though...

Another DIY:er made an simulation of the Helmke circuitry. I think the gain was about 1.5 times. That will correspond to 12 mV/94 dB. A lot more than the original 1.6 mV. The noisy floor of my soundcard, would probably not be a problem then. Your circuitry have perhaps simular gain?

Roger

The gain of the circuit I simulated was about .7 and I think that's the gain of the Helmke circuit too.

[Roger Gustavsson]

Thank you, SparkE!

So there is no gain. Your circuitry even reduces the output somewhat? But there are two out of phase signals, would it not mean that these should be added to each other? The output impedance will at least be low?

[SparkE!]

Thank you, SparkE!

So there is no gain. Your circuitry even reduces the output somewhat? But there are two out of phase signals, would it not mean that these should be added to each other? The output impedance will at least be low?

I'm including the gain associated with adding the two outputs.  The main advantages you get from this type of topology are the differential output, low distortion and low output impedance.  So, you can drive longer cables without much degradation, except due to resistive losses in the cable.

[Roger Gustavsson]

But there will still be 10-11 dB more level from this circuitry than the original Nakamichi with its output transformer. Not a bad thing!

I have been told elsewhere that the schematic E in the beginning of this thread, should have drain and source resistors in the range 2-3 kOhm for a 9V supply. Would give an output impedance of 590-650 Ohm. Could still drive up to 2 nF of cable capacitance? Can you say if the output level will change from the schematic C or D?

[SparkE!]

No, I think that if you use 2k to 3k, it will give each output an impedance of 2k to 3k in schematic E.

Schematics C and D will give a lower output impedance at the expense of higher harmonic distortion.

[Roger Gustavsson]

So the simulation below with a different JFET is all wrong? Load is 10 nF and 10 kOhm.

[SparkE!]

Well, according to the upper cuttoff frequency shown in your simulation, that appears to have an output impedance of about 122 ohms per side, so I guess I had that wrong...  I was thinking that the output impedance would be dominated by the drain and source resistors.

[Roger Gustavsson]

The schematic C will give this: 1/gm // R source

(1/1.2ms) // 1200 = 492 Ohm

I have no idea of the phase splitted output, like in E but with source and drain resistors = 2 kOhm. Maybe the different legs will be (1/1.2ms) // 2000 = 588 Ohm, using the same formula?

[SparkE!]

When I load the output of the circuit that I simulated (NakMod.jpg) with a 10 nF cap, it implies an output impedance of about 13 ohms per side. So I guess that the emitter follower amps further reduce the output impedance.

Also, I changed my JFET model to the JFET you are using and the gain went up to 1.4, so that's about a 3 dB gain.  The harmonic distortion is about 0.5% at 1 kHz.

[Roger Gustavsson]

Thank you for helping me out!

0.5% distorsion at what level? Are we talking input or output level? My recording situation seldom sees anything above 100 dB. Sure your circuitry should lower the output impedance compared to the nonbuffered one. 

[SparkE!]

I was using 1.6 mV at the input since that is what you had mentioned previously.  I don't know what signal level to use.

[Roger Gustavsson]

0.5% is high compared to the modified P93 http://taperssection.com/index.php?action=dlattach;topic=87397.0;attach=67399. It seems to have 0.024% at 8 mV input and 208 mV output. It takes up more space than your circuitry.

[SparkE!]

I'm not sure if I'm buying that claim of .024% distortion.  Is that what you're getting from a simulation?  What version of SPICE are you using?